Power optimized packet buffering in a protocol processor

In the emerging research area of protocol processors (PP) there exist many hardware platform proposals. One example of such a platform solution has been proposed by the author in a series of papers, mainly focusing on datapath organization and optimization. The proposed platform is unique since the fast path process incoming packets before storage in the input buffer. This paper proposes that a FIFO buffer should be added to the input buffer to lower the power consumption. The optimization process and the optimal input buffer architecture are dependent on a large number of parameters, e.g. network type and traffic, host system and physical implementation process. Simulating energy consumption characteristics, a number of architectural conclusions have been made. Especially an input packet buffer configuration is proposed which can be used in a wide variety of network applications and host systems.